library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity cun is
	port (
		Aresult  : in std_logic_vector(47 downto 0);
		Bresult  : in std_logic_vector(47 downto 0);
		Cresult  : in std_logic_vector(47 downto 0);
		Aemptyall: in std_logic;
		Bemptyall: in std_logic;
		Cemptyall: in std_logic;
		Aemptyone: in std_logic;
		Bemptyone: in std_logic;
		Cemptyone: in std_logic;
		Arequestrd : out std_logic;
		Brequestrd : out std_logic;
		Crequestrd : out std_logic;
		writereq   : out std_logic;
		newframe   : out std_logic;
		result     : out std_logic_vector(47 downto 0));
end cun;

architecture RTL of cun is
	signal en: std_logic;
	signal req: std_logic_vector(1 downto 0);
begin
	process(Aemptyall, Bemptyall, Cemptyall, Aemptyone, Bemptyone, Cemptyone)
	begin
		en  <= Aemptyall or Bemptyall or Cemptyall;
		if (en = '0') then
		   req <= "00";
		else
		if(Aemptyone = '0') then
				req <= "01";
		else if(Bemptyone = '0') then
				req <= "10";
		else if(Cemptyone = '0') then
				req <= "00";
		end if;
		end if;
		end if;
		end if;
		if (en = '1') then
			if (req = "00")then
				Arequestrd <= '1';
				Brequestrd <= '0';
				Crequestrd <= '0';
				result <= Aresult;
				writereq <= '1';
				newframe <= '1';
			elsif (req = "01" ) then
				Arequestrd <= '0';
				Brequestrd <= '1';
				Crequestrd <= '0';
				result <= Bresult;
				writereq <= '1';
				newframe <= '1';
			elsif (req = "10") then
				Arequestrd <= '0';
				Brequestrd <= '0';
				Crequestrd <= '1';
				result <= Cresult;
				writereq <= '1';
				newframe <= '1';
			else
				Arequestrd <= '0';
				Brequestrd <= '0';
				Crequestrd <= '0';
				writereq <= '0';
				newframe <= '0';
			end if;
		else 
			Arequestrd <= '0';
			Brequestrd <= '0';
			Crequestrd <= '0';
		end if;
 	end process;
end RTL;